Clarification on branch instruction when Register value is 0



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Clarification on branch instruction when Register value is 0

Postby ramkumar1992sp » Fri Mar 03, 2017 3:32 am

Hello Experts,


         SLL   R9,1                      
         LTR   R9,R9                    
         BZ    NXTMEET
         BP    NXTSEM
 


Suppose R9 has a value of 8. i.e. 10000000 00000000 00000000 00000000

When the first SLL R9,1 is executed,then both the above branch statements will be skipped since sign bit is negative.

Now for the second SLL R9,1 Can someone please tell me which Branch Instruction will be executed,since R9 now contains a value of 0 and also the bit 0 is 0 so positive.
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Re: Clarification on branch instruction when Register value is 0

 

Re: Clarification on branch instruction when Register value

Postby ramkumar1992sp » Fri Mar 03, 2017 3:41 am

Correction :
Please disregard value of "8" here,I meant a value of 2^31
Suppose R9 has a value of 8. i.e. 10000000 00000000 00000000 00000000
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Re: Clarification on branch instruction when Register value

Postby Robert Sample » Fri Mar 03, 2017 4:06 am

Did you check the Principles of Operation manual to see what it says? If not, why not -- it should always be your FIRST reference for such questions?
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Re: Clarification on branch instruction when Register value

Postby steve-myers » Fri Mar 03, 2017 7:43 am

The title is poor, as register 9 is not part of the branch instructions, either as a base register or an index register. Well, probably not as a base register since we do not know the USING, and an index register is not specified in either branch instruction.

What the topic starter is really asking here is, "what will be the contents of register 9 after the SLL instruction completes?" In other words, what happens to the 1 bit in bit 32 (using the IBM bit position nomenclature).

As Mr. Sample says, "What does Principles of Operation say?

Actually, it does not seem to explicitly say. We can make inferences from things it does say, like "Bits 0-31 of general register R1 remain unchanged." From that we can infer that bit 32 does not move to bit position 31. The 1 in R1 is a subscript in Principles of Operation, but it does not come through in the copy/paste. It does say, "For SLL, the first operand is in bit positions 32-63 of general register R1. All 32 bits of the operand participate in the left shift." About all we can infer from this is the 1 bit will be discarded, so what does this mean for bit 63. Well, Principle of Operation does say, "For SLL, SLLG, or SLLK, zeros are supplied to the vacated bit positions on the right." (SLL is discussed with SLLG and SLLK.)

Now given all this, I'm sure the topic starter can infer what will be in register 9 after the SLL completes.
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Re: Clarification on branch instruction when Register value

Postby ramkumar1992sp » Fri Mar 03, 2017 10:42 am

Thank you Robert and Steve for the response.

I think I understand how SLL works.My question was in regards to how to differentiate between BZ and BP in scenarios when the register content becomes zero as a bit is shifted left.

In the example that I gave earlier

"Suppose R9 has a value of 2^31. i.e. 10000000 00000000 00000000 00000000).Here the 1-bit(sign bit is 1)(bit 32 of 64 bit register) so the number is negative.So both BZ and BP are skipped..


But imagine that piece of code is called in a loop so during the next iteration this bit 1 is discarded and the contents in that register will have a value of zero. My question is at this point whether BZ would be executed or the BP ?

I think BZ would be executed since I think 0 is not positive.But I haven't got a confirmation on this after reading the POP manual..

Below is explanation of LTR from POP.
"
The second operand is placed unchanged at the first-operand location, except that, for LOAD AND
TEST (LTGFR), it is sign extended. The sign and
magnitude of the second operand, treated as a
signed binary integer, are indicated in the condition
code.



Resulting Condition Code:

0 Result zero

1 Result less than zero

2 Result greater than zero

3 -- "


The reason I ask this is I was thinking about difference of getting a value of zero after 32 iterations of SLL and in scenarios where the register value become zero just after a few execution of SLL based on the contents of the register.

I'm not very sure if I was able to convey my question clearly.

Thanks.
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Re: Clarification on branch instruction when Register value

Postby steve-myers » Fri Mar 03, 2017 11:54 am

First, you are confusing the strict mathematical condition code setting with the actual condition code setting. In strict arithmetic, a 0 value is positive, so BP should branch. Now look at the resulting condition code settings. 0 sets condition code 0. Since (for example) 1 is greater than 0, LTR sets condition code 2, so BZ won't branch, but BP will branch. There is no extended branch mnemonic for branch 0 or positive, though if you want to be picky and follow strict arithmetic rules, BP probably should be BC B'1010' rather than BC B'0010'. Problem is few would want that, and it's too late, anyway. The way it's set up now, it's easier (and probably more useful) to distinguish between 0 and all other positive numbers.

LTR does not set CC 3. CC 3 is usually reserved for overflow, though TM (and a few other instructions) can set it in normal operation. If you think about, you'll realize LTR isn't going to overflow, so it has no occasion to set CC 3.
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Re: Clarification on branch instruction when Register value

Postby ramkumar1992sp » Fri Mar 03, 2017 8:23 pm

Thank you Steve for the response.

I found this in POP under "Binary-Integer Representation " and it looks like this answers my question.I'm sorry I didnt know what exactly to look for till now when I was searching POP.


"For signed binary integers, the leftmost bit represents
the sign, which is followed by the numeric field. Positive
numbers are represented in true binary notation
with the sign bit set to zero. When the value is zero,
all bits are zeros, including the sign bit. Negative
numbers are represented in two’s-complement
binary notation with a one in the sign-bit position. "

 


So now when SLL R9,1 is executed with value of
R9 as 10000000 00000000 00000000 00000000, the BZ will be executed as all bits are zero including the sign-bit.

Suppose R9 has a value of 10000000 00000000 00000000 10000000
then after SLL R9,1, BP will be executed as the new sign-bit is 0 and the value in the remaining bits is positive.
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Re: Clarification on branch instruction when Register value

Postby steve-myers » Sat Mar 04, 2017 3:11 am

ramkumar1992sp wrote:... So now when SLL R9,1 is executed with value of
R9 as 10000000 00000000 00000000 00000000, the BZ will be executed as all bits are zero including the sign-bit.

SLL does not alter the condition code. It won't be changed until the LTR instruction executes.
ramkumar1992sp wrote:... Suppose R9 has a value of 10000000 00000000 00000000 10000000
then after SLL R9,1, BP will be executed as the new sign-bit is 0 and the value in the remaining bits is positive.

As before, SLL does not alter the condition code. By the way, while BP implies "positive," it's really greater than 0. which takes the idea the 0 is positive out of the picture.

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Re: Clarification on branch instruction when Register value

Postby ramkumar1992sp » Sat Mar 04, 2017 3:20 am

Thanks Steve.
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Re: Clarification on branch instruction when Register value

Postby steve-myers » Sat Mar 04, 2017 11:21 am

Actually the topic starter has pointed out an interesting anomaly. Suppose the register is 80000000 (10000000 00000000 00000000 00000000) when the LTR executes. Since we are thinking a logical value, we would expect CC 2, but LTR is going to set CC 1 because the value is negative. So neither BP or BZ are going to branch.

I thought AL reg,=F'0' would set CC 2, but I was wrong; it sets CC = 1 (result not 0, no carry). AL does set CC = 2 (result zero;carry), but that's not terribly useful for us.

Since there seems to be no better alternative, though (in my opinion) it fails a self documentation requirement, about all we can do is LTR / BZ / BNZ.
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