bobguo wrote:but now, the instruction LA can load 31 bits(or 32 bits, i'm not sure) into one register, so does LA change during these 40 years? Otherwise, we can not explain why it can load 31/32 bits now from original 24 bits.
In the System/360, and the System/370 (and in the 24-bit AMODE), LA does the 24-bit address computation, stores the result in bits 8 through 31, and sets the high order bits of the register to 0. It was common to see LA x,0(,x) used to set bits 0 through 7 of a register to 0. Instructions like EDMK and TRT stored an address in bits 8 to 31 and did not alter bits 0 through 7 of register 1. In the 31-bit addressing mode, LA does the 31 bit address computation, stores the calculated address in bits 1 through 31, and sets bit 0 to 0. In the 31-bit addressing mode, TRT and EDMK store the 31-bit address and do not alter bit 0.
BAL/BALR also changed, and the BAS/BASR instructions were added. I first encountered BAS/BASR on the Model 20 and were also added to the Model 67. BAS/BASR were RPQ instructions in the 370/168 so TSS/370, the System/370 version of the TSS/360 more or less failed operating system could run. In the System/360, and the original System/370, BAL/BALR store the entire low order 32 bits of the PSW into the link register, so bits 0 through 7 were set to the instruction length code, the condition code, and the interrupt mask. In the 24-bit addressing mode, these data areas are collected and stored into the link register.
A quick quiz for you. In the R form GETMAIN macro, you see
Why is the instruction there? What happens in the 31-bit addressing mode?